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description features sy87701v 3.3v and 5v power supply options clock and data recovery from 32mbps up to 1.25gbps nrz data stream complies with bellcore, itu/ccitt and ansi specifications for applications such as oc-1, oc-3, oc-12, atm, fddi, etc. two on-chip plls: one for clock generation and another for clock recovery selectable reference frequencies differential pecl high-speed serial i/o line receiver input: no external buffering needed link fault indication 100k ecl compatible i/o available in 28-pin soic and 32-pin ep-tqfp packages the sy87701v is a complete clock recovery and data retiming integrated circuit for data rates from 32mbps up to 1.25gbps nrz. the device is ideally suited for sonet/sdh/atm and fibre channel applications and other high-speed data transmission systems. clock recovery and data retiming is performed by synchronizing the on-chip vco directly to the incoming data stream. the vco center frequency is controlled by the reference clock frequency and the selected divide ratio. on-chip clock generation is performed through the use of a frequency multiplier pll with a byte rate source as reference. the sy87701v also includes a link fault detection circuit. 5v/3.3v 32-1250mbps anyrate clock and data recovery applications sonet/sdh/atm oc-1, oc-3, oc-12, oc-24 fibre channel, escon gigabit ethernet/fast ethernet proprietary architecture up to 1.25gbps phase detector phase/ frequency detector charge pump vco charge pump vco link fault detector divider by 8, 10, 16, 20 refclk cd rdinn rdinp pllr p/n clksel rdoutp rclkp rclkn rdoutn lfin freqsel 1/2/3 plls p/n divsel 1/2 sy87701v tclkp tclkn v cc v cca v cco gnd 1 0 (pecl) (pecl) (ttl) (ttl) (pecl) (ttl) (pecl) (pecl) (ttl) (ttl) 0 1 phase/ frequency detector block diagram 1 rev.: h amendment: /0 issue date: september 2000 anyrate is a trademark of micrel, inc.
sy87701v 2 micrel pin descriptions inputs rdinp, rdinn [serial data input] differential pecl. these built-in line receiver inputs are connected to the differential receive serial data stream. an internal receive pll recovers the embedded clock (rclk) and data (rdout) information. the incoming data rate can be within one of eight frequency ranges depending on the state of the freqsel pins. see ?requency selection?table. refclk [reference clock] ttl input. this input is used as the reference for the internal frequency synthesizer and the ?raining?frequency for the receiver pll to keep it centered in the absence of data coming in on the rdin inputs. cd [carrier detect] pecl input. this input controls the recovery function of the receive pll and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. when this input is high the input data stream (rdin) is recovered normally by the receive pll. when this input is low the data on the inputs rdin will be internally forced to a constant low, the data outputs rdout will remain low, the link fault indicator output lfin forced low and the clock recovery pll forced to lock onto the clock frequency generated from refclk. pllsp tclkn 18 11 pllsn clksel 17 12 gnd pllrp 16 13 gnd pllrn 15 14 1 vcca lfin divsel1 rdinp rdinn freqsel1 refclk freqsel2 freqsel3 n/c 28 vcc cd divsel2 rdoutp rdoutn vcco rclkp rclkn vcco tclkp 27 26 25 24 23 22 21 20 19 2 3 4 5 6 7 8 9 10 top view soic z28-1 pin configuration 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc rdinp rdinn freqsel1 refclk freqsel2 freqsel3 nc rdoutp rdoutn vcco rclkp rclkn vcco tclkp tclkn 9 10 11 12 13 14 15 16 clksel pllrp pllrn gnd gnd gnda pllsn pllsp 32 31 30 29 28 27 26 25 divsel2 cd vcc vcc vcca vcca lfin divsel1 top view ep-tqfp h32-1 freqsel1, ..., freqsel3 [frequency select] ttl inputs. these inputs select the output clock frequency range as shown in the frequency selection table. divsel1, divsel2 [divider select] ttl inputs. these inputs select the ratio between the output clock frequency (rclk/tclk) and the refclk input frequency as shown in the reference frequency selection table. clksel [clock select] ttl input. this input is used to select either the recovered clock of the receiver pll (clksel = high) or the clock of the frequency synthesizer (clksel = low) to the tclk outputs. outputs lfin [link fault indicator] ttl output. this output indicates the status of the input data stream rdin. active high signal is indicating when the internal clock recovery pll has locked onto the incoming data stream. lfin will go high if cd is high and rdin is within the frequency range of the receive pll (1000ppm). lfin is an asynchronous output.
sy87701v 3 micrel functional description clock recovery clock recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. the clock is phase aligned by a pll so that it samples the data in the center of the data eye pattern. the phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. output pulses from the detector indicate the required direction of phase correction. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which generates the recovered clock. frequency stability without incoming data is guaranteed by an alternate reference input (refclk) that the pll locks onto when data is lost. if the frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the pll will be declared out of lock, and the pll will lock to the reference clock. the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. this transfer function yields a 30 s data stream of continuous 1's or 0's for random incoming nrz data. the total loop dynamics of the clock recovery pll provides jitter tolerance which is better than the specified tolerance in gr-253-core. lock detect the sy87701v contains a link fault indication circuit which monitors the integrity of the serial data inputs. if the received serial data fails the frequency test, the pll will be forced to lock to the local reference clock. this will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. if the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the pll will be declared out of lock. the lock detect circuit will pull the input data stream in an attempt to reacquire lock to data. if the recovered clock frequency is determined to be within approximately 1000ppm, the pll will be declared in lock and the lock detect output will go active. rdoutp, rdoutn [receive data output] differential pecl. these ecl 100k outputs (+3.3v or +5v referenced) represent the recovered data from the input data stream (rdin). this recovered data is sampled on the rising edge of rclk. rclkp, rclkn [clock output] differential pecl. these ecl 100k outputs (+3.3v or +5v referenced) represent the recovered clock used to sample the recovered data (rdout). tclkp, tclkn [clock output] differential pecl. these ecl 100k outputs (+3.3v or +5v referenced) represent either the recovered clock (clksel = high) used to sample the recovered data (rdout) or the transmit clock of the frequency synthesizer (clksel = low). pllsp, pllsn [clock synthesis pll loop filter] external loop filter pins for the clock synthesis pll. pllrp, pllrn [clock recovery pll loop filter] external loop filter pins for the receiver pll. power & ground v cc supply voltage (1) v cca analog supply voltage (1) v cco output supply voltage (1) gnd ground n/c no connect note: 1. v cc , v cca , v cco must be the same value.
sy87701v 4 micrel characteristics performance the sy87701v pll complies with the jitter specifications proposed for sonet/sdh equipment defined by the bellcore specifications: gr-253-core, issue 2, december 1995 and itu-t recommendations: g.958 document, when used with differential inputs and outputs. input jitter tolerance input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1db optical/electrical power penalty. sonet input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1db power penalty. figure 1. input jitter tolerance oc/sts-n f0 f1 f2 f3 ft level (hz) (hz) (hz) (khz) (khz) 3 10 30 300 6.5 65 12 10 30 300 25 250 15 1.5 0.40 f0 f1 f2 f4 ft sinusoidal input jitter amplitude (ui p-p) frequency -20db/decade -20db/decade a figure 2. jitter transfer oc/sts-n fc p level (khz) (db) 3 130 0.1 12 225 0.1 0.1 -20 fc jitter transfer (db) fre q uenc y -20db/decade acceptable range jitter transfer jitter transfer function is defined as the ratio of jitter on the output oc-n/sts-n signal to the jitter applied on the input oc-n/sts-n signal versus frequency. jitter transfer requirements are shown in figure 2. jitter generation the jitter of the serial clock and serial data outputs shall not exceed .01 u.i. rms when a serial data input with no jitter is presented to the serial data inputs.
sy87701v 5 micrel frequency selection table freqsel1 freqsel2 freqsel3 f vco /f rclk f rclk data rates (mbps) 0 0 0 1 750 1250 0 0 1 2 375 625 0 1 0 4 188 313 0 1 1 6 125 208 1 0 0 8 94 157 1 0 1 12 63 104 1 1 0 16 47 78 1 1 1 24 32 52 divsel1 divsel2 f rclk /f refclk 00 8 01 10 10 16 11 20 reference frequency selection symbol rating value unit v cc power supply 0.5 to +7.0 v v i input voltage 0.5 to v cc v i out output current ma continuous 50 surge 100 t store storage temperature 65 to +150 c t a operating temperature 0 to +85 c ja thermal resistance 80 single c/w @still air layer board, 46 multi-layer notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. airflow of 500lfpm recommended. absolute maximum ratings (1, 2) loop filter components (1) r5 c3 pllsp pllsn sonet wide range r6 = 50 ? r6 = 680 ? c4 = 1.0 f (x7r dielectric) c4 = 0.47 f (x7r dielectric) r6 c4 pllrp pllrn note: 1. suggested values. values may vary for different applications. sonet wide range r5 = 80 ? r5 = 350 ? c3 = 1.5 f (x7r dielectric) c3 = 0.47 f (x7r dielectric)
sy87701v 6 micrel symbol parameter min. typ. max. unit condition f vco vco center frequency 750 1250 mhz f refclk * byte rate ? f vco vco center frequency 5 % nominal tolerance t acq acquisition lock time 15 s t cpwh refclk pulse width high 4 ns t cpwl refclk pulse width low 4 ns t ir refclk input rise time 0.5 2 ns t odc output duty cycle (rclk/tclk) 45 55 % of ui t r , t f ecl output rise/fall time 100 500 ps 50 ? to v cc 2 (20% to 80%) t skew recovered clock skew 200 +200 ps t dv data valid 1/(2*f rclk) 200 ps t dh data hold 1/(2*f rclk) 200 ps symbol parameter min. typ. max. unit condition v ih input high voltage 2.0 v cc v v il input low voltage 0.8 v i ih input high current 175 av in = 2.7v, v cc = max. +100 av in = v cc, v cc = max. i il input low current 300 av in = 0.5v, v cc = max. v oh output high voltage 2.0 vi oh = 0.4ma v ol output low voltage 0.5 v i ol = 4ma i os output short circuit current 15 100 ma v out = 0v (maximum 1sec) v cc = v cco = v cca = 3.3v 5% or 5.0v 5%; t a = 0 c to +85 c ttl dc electrical characteristics v cc = v cco = v cca = 3.3v 5% or 5.0v 5%; t a = 0 c to +85 c ac electrical characteristics symbol parameter min. typ. max. unit condition v ih input high voltage v cc - 1.165 v cc - 0.880 v v il input low voltage v cc - 1.810 v cc - 1.475 v i il input low current 0.5 av in = v il (min.) v oh output high voltage v cc - 1.075 v cc - 0.830 v 50 ? to v cc 2v v ol output low voltage v cc - 1.860 v cc - 1.570 v 50 ? to v cc 2v v cc = v cco = v cca = 3.3v 5% or 5.0v 5%; t a = 0 c to +85 c pecl 100k dc electrical characteristics symbol parameter min. typ. max. unit condition v cc power supply voltage 3.15 3.3 3.45 v 4.75 5.0 5.25 v i cc power supply current 170 230 ma dc electrical characteristics
sy87701v 7 micrel timing waveforms t cpwl t cpwh rdout rclk refclk t odc t odc t skew t dv t dh
sy87701v 8 micrel application example for ac coupling only when vcc = +5v when vcc = +3.3v c1 = c2 = 0.1 f c1 = c2 = 0.1 f r1 = r2 = 1.2k ? r1 = r2 = 680 ? r3 = r4 = 3.4k ? r3 = r4 = 1k ? table 1. for dc mode only when vcc = +5v when vcc = +3.3v c1 = c2 = shorted c1 = c2 = shorted r1 = r2 = 82 ? r1 = r2 = 130 ? r3 = r4 = 130 ? r3 = r4 = 82 ? sw1 gnd 123456 divsel1 vcc rdoutp 1 2 3 4 5 12 6 11 7 10 8 9 divsel2 rdinp lfin rdinn vcca freqsel1 refclk cd rdoutn vcco rclkp rclkn freqsel2 17 18 19 20 21 22 23 24 25 26 27 28 pllsp pllsn n/c freqsel3 vcco tclkp tclkn clksel 13 16 gnd pllrp 14 15 gnd pllrn c3 r5 80 ? 1.5 f gnd c4 r6 50 ? 1.0 f vcc vcc gnd r2 r1 r3 r4 c9 0.1 f c8 22 f c7 0.1 f c6 22 f ferrite bead blm21a102 fb1 (r17 - r22) 5k ? x 6 diode d1 1n4148 c14 0.1 f c15 c16 c17 c18 c19 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f r11 r12 r13 r14 r15 r16 capacitor pads (1206 format) rdin c1 c2 0.1 f c13 14 8 1 7 120 ? r23 vcc nc dpdt slide switch refclk (ttl) loop filter network vcc stand off r7 xtal oscillator if vcc = +5v: r9 through r14 = 330 ? if vcc = +3.3v: r9 through r14 = 220 ? see table 1 j1 r8 vcc r10 q1 2n2222a led d2 r9 vcc gnd pin 1 (vcca) pin 28 (vcc) pin 23 (vcco) pin 20 (vcco) c5 c10 c11 c12 0.1 f 0.1 f 0.1 f 0.1 f vcc note: 1. c5 and c10 c12 are decoupling capacitors and should be kept as close to the power pins as possible.
sy87701v 9 micrel ordering package operating code type range sy87701vzc z28-1 commercial SY87701VHC h32-1* commercial product ordering code *contact factory for availability. material list for bypass and ac coupling capacitor, high quality factor (high q) capacitors are recommended. this will optimize the performance of the device in high frequency domain. description component part no. (1, 2) sy87700l/sy87700v/sy87701l/sy87701v u1 80 ? plls+, r5 1.5 f plls , c3 50 ? pllr+, r6 1.0 f pllr , c4 5k ? or 4.7k ? pull up resistor x 6, r17 r22 330 ? or 220 ? (see schematic) output pull down resistor, r11 r16 4.7k ? pull up resistor, r7 130 ? pull up resistor, r9 12k ? pull down resistor, r8 12k ? r10 120 ? r23 0.1 f ac coupling capacitors x 6, c1, c2, c14 c19 tantalum, 22 f, 16v decoupling capacitor, c6, c8 0.1 f decoupling capacitors x 7, c5, c7, c9 c13 murata blm21a102f ferrite bead, fb1 1n4148 diode, d1 johnson smas, id#142-0701-201 smas x 9 6-pin dip switch sw1 dpdt slide switch led the suggested dielectric characteristics for these capacitors are npo and/or cog. avx is a suggested provider of electronic components. www.avxcorp.com notes: 1. for v cc = 3.3v r8 = 12k ? ; r = 130 ? 2. for v cc = 5.0v r8 = 24k ? ; r9 = 200 ?
sy87701v 10 micrel 28 lead soic .300" wide (z28-1) rev. 02
sy87701v 11 micrel 32 lead epad tqfp (die up) (h32-1) rev. 01
sy87701v 12 micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated

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